1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly relates to a semiconductor device that generates a clock signal when it is required.
2. Description of Related Art
Recently, DDR (Double Data Rate) type synchronous memory device used as main memory of a personal computer or the like has been used in many cases as a semiconductor device which performs an operation in synchronization with a high-speed clock signal. For such semiconductor devices, a configuration in which output timing of read data is synchronized with an external clock signal is employed. According to this configuration, data transmission/reception between a controller and a semiconductor device can be performed at timing synchronized with the external clock signal. Therefore, data transmission/reception to each other is performed without an error. By the way, since internal delay is present in the semiconductor device itself, it is necessary to generate an internal clock signal inside the semiconductor device so that the output timing of the read data can be synchronized with the external clock signal while considering the delay time. The circuit realizing that is a DLL (Delay Locked Loop) circuit.
An example of the DLL circuit is disclosed in Japanese Patent Application Laid-open No. 2009-278528. This patent application discloses stopping an operation of a DLL circuit so as to reduce power consumption of the DLL circuit during a refresh operation e.g. in which an internal clock is not used.
However, the background technique described above has a problem that aging degradation of a large number of CMOSs (Complementary Metal Oxide Semiconductors; hereinafter, these CMOSs are collectively referred to as “drive circuit”) that exist on a transmission path of an internal clock signal is expedited. That is, because the internal clock signal is fixed to logical high (or logical low) even when the operation of the DLL circuit is stopped, each node in the drive circuit becomes fixed to high or low. Each of a P-channel MOS transistor and an N-channel MOS transistor that constitute each CMOS has a characteristic that the threshold voltage increases gradually as an ON state continues. This characteristic is referred to as “NBTI” (Negative Bias Temperature Instability) in the P-channel MOS transistor and “hot carrier degradation” in the N-channel MOS transistor. Due to this characteristic of each transistor, during an output of the DLL circuit is fixed to low, for example, the threshold voltage of each transistor on a side where the ON state continues increases, which causes aging degradation of the drive circuit. On the other hand, the threshold voltage of each transistor on a side where an OFF state continues is not relatively degraded. This means one of the MOS transistors in a CMOS (for example, a P-channel MOS transistor) is degraded due to the continued ON state while the other transistor (for example, an N-channel MOS transistor) is not degraded due to the continued OFF state and causes a problem such as a distortion of a duty cycle of a clock to be transmitted.
Such aging degradation of a drive circuit occurs not only in a DLL circuit for synchronizing an output timing of read data with an external clock signal. That is, even in some other types of clock generation circuits, if the generation of a clock is stopped for a certain extent of long time, similar aging degradation can occur in a drive circuit that receives a clock signal from the clock generation circuit. In addition, similar aging degradation occurs not only when the output is fixed to low, but also when it is fixed to high. Therefore, there has been a demand for a technique which can suppress aging degradation of a drive circuit that receives a clock signal from a clock generation circuit in which the generation of a clock is possibly stopped and its output is fixed to high or low.